1. Field of the Invention
The embodiments of the invention generally relate to methods and systems for performing timing analysis and, more specifically, to methods, systems, and integrated circuit structures that separately test the timing characteristics within clock domains and timing characteristics between clock domains by selectively blocking or unblocking the inputs to clock domains.
2. Description of the Related Art
When performing timing analysis on integrated circuit structures (such as integrated circuit chips) traditional edge based multiplexer scan architectures can be exposed to race conditions at the interfaces between clock domains. A clock domain is a grouping of circuit structures (e.g., flip flops) that are driven by a common clock signal. A race condition or race hazard is a flaw in a system or process whereby the output and/or result of the process is unexpectedly and critically dependent on the sequence or timing of other events. The term originates with the idea of two signals racing each other to influence the output first. Race conditions can produce unpredictable results as the output may not be based upon logic, but instead may simply be based on which signal reaches a destination first.
Known solutions to race hazards include additional timing constraints where the race conditions are corrected for timing. However, such solutions are difficult to implement and add to the time needed to design the chip. Further, with conventional testing, the chip is tested one domain at a time, which adds to test patterns and test time and thus adversely impacts manufacturing cost.
Some testing systems, such as an Automatic Test Pattern Generation Tool, do not perform timing testing at domain crossings, which results in loss of test coverage at such domain crossings. Other systems such as Logic Built-In Self Test (BIST) methodologies, for which patterns are randomly generated on-chip, cannot accommodate race hazards because it is not possible to modify the random patterns in a way that would prevent transitions at domain crossings.